Estimation of Round-Off Errors on Several Computer Architectures
نویسندگان
چکیده
Numerical validation of computed results in scienti c computation is always an essential problem as well on sequential architecture as on parallel architecture. The probabilistic approach is the only one that allows to estimate the round-o error propagation of the oating point arithmetic on computers. We begin by recalling the basics of the CESTAC method (Contrôle et Estimation STochastique des Arrondis de Calculs). Then, the use of the CADNA software (Control of Accuracy and Debugging For Numerical Applications) is presented for numerical validation on sequential architecture. On parallel architecture, we present two solutions for the control of round-o errors. The rst one is the combination of CADNA and the PVM library. This solution allows to control round-o errors of parallel codes with the same architecture. It does not need more processors than the classical parallel code. The second solution is represented by the RAPP prototype. In this approach, the CESTAC method is directly parallelized. It works both on sequential and parallel programs. The essential di erence is that this solution requires more processors than the classical codes. These di erent approaches are tested on sequential and parallel programs of multiplication of matrices.
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عنوان ژورنال:
- J. UCS
دوره 1 شماره
صفحات -
تاریخ انتشار 1995